3D Integration (Design for Test) Engineer

Our client, a leading technology company, is seeking a talented 3D Integration (Design for Test) engineer to join their team. This is an exciting opportunity to work on cutting-edge research and development in the field of semiconductor design and testing.

Role Description

As the 3D Integration (Design for Test) engineer, you will be responsible for conducting research on DFT (Design for Test) methodologies for digital logic chips, focusing on defect mechanisms, fault simulation, and failure analysis. You will also develop DFT testing methodologies for 3DIC chips and explore DFT testing approaches for Memory, emerging NVM (Non-Volatile Memory), and analog IP.

Must Have Skills

• Familiar with DFT technologies such as MBIST, SCAN, and ATPG, as well as semiconductor manufacturing processes and device structures.
• Knowledge of digital and analog circuit failure mechanisms, fault modelling, and test algorithms.
• Research experience in digital circuit defect mechanisms, fault simulation, and failure analysis.
• Research experience in 3DIC and IO interconnect defects, fault simulation, and failure analysis.
• Research experience related to memory or analog circuit defect modelling, simulation, and failure analysis.
• Experience in system-level DFX implementation, protection strategies, and failure localization techniques.

Nice to Have Skills

• Master’s degree or above in Electronics, Microelectronics, Communications, Automation, Semiconductor Engineering, Mathematics, Physics, Chemistry, or related fields.
• 5–10 years of relevant experience.

Job Ref : BBBH26034

Next Steps

If you believe you have the necessary skills and experience to excel in this 3D Integration (Design for Test) engineer role, we encourage you to submit your CV today. Our dedicated team will review your application and be in touch to discuss the next steps.

Interested in this Role?