Senior Digital ASIC Design Engineer — RTL & Verification

A high-tech consultancy company in Brussels is seeking a Digital ASIC Design Engineer. This role involves the design, verification, and implementation of innovative digital ASICs. Candidates should have a Master's degree in Electronics and at least 5 years of experience in RTL design using Verilog / SystemVerilog or VHDL. Proficiency with EDA tools is essential, and fluency in English is required. The position promises a stimulating work environment where you can direct your own career as part of a supportive culture.

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