Senior Digital Design Verification Engineer

We have had a great opportunity for a Senior Digital Design Verification Engineer in Belgium.

Job Title : Senior Digital Design Verification Engineer

Location : Leuven, Belgium – minimum 3 days in office

Type : Freelancer | 100% FTE (40 hours / week)

Duration : 6 months

Start Date : 12 Jan 2026

Hourly rate : €60–75 / hour

Key Skills :

UVM

SystemVerilog

Assertion-Based Verification

5–10 years’ experience in digital IC design / verification

Role Overview :

We are building a new product development team in Leuven and seek a skilled engineer in digital IC hardware verification . The role involves verifying blocks, subsystems, or top-level functions, developing testbenches, and collaborating with cross-functional teams to ensure product success.

Responsibilities :

• Own verification of assigned blocks / subsystems
• Develop and implement testcases using SystemVerilog, UVM, Python, and assertions
• Maximize verification coverage and maintain regression suites
• Participate in design reviews, peer reviews, and root-cause analysis
• Collaborate with other teams (Analog, Firmware, Layout)

Candidate Profile :

• Master’s in Electronic / Electrical Engineering
• Proven experience delivering high-volume silicon
• Knowledge of low-power design techniques; audio / AI accelerators a plus
• Familiar with Cadence EDA tools , Synopsys Spyglass , VHDL / Verilog / SystemVerilog, Python
• Strong analytical, debugging, and hands-on skills
• Team player with excellent communication; fluent in English

If you could be interested, please get in touch and share your CV with me tee@microtech-global.com