As a Senior FPGA Engineer, you will contribute to the development of key components of our networking system, including SmartNICs and hybrid optical switches. You will be responsible for designing and optimizing VHDL and/or Verilog implementations. In the next phase, you will verify your designs in simulation by writing test cases and scenarioʼs within our Python simulation environment. You will integrate your designs and IP cores into our FPGA projects. Next to this, timing analysis and on-target verification are key responsibilities of this role.
Finally, you will participate in the system level performance testing and debug fixing in close collaboration with the software and networking team.
Requirements
Must-have
Nice-to-have
The working mode is hybrid. Consultants must be based close to the client's premises.
Senior FPGA Engineer (VHDL/Verilog) • Schelle, Flanders, BE
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